Fiber optic waveguides enable the serial transmission of information from a driver to a receiver at a relatively long distance (kilometers) and at very high data rates (billions of bits per second). High performance data processing complexes require system buses among their elements to have very high bandwidths of information transfer (100's of millions of bytes per second). The use of a single conductor, such as a fiber optic waveguide, can be insufficient to serve as such a system bus because of bandwidth limitations.
In the prior art, one solution to the bandwidth problem has been to use multiple conductors in parallel, each conductor carrying a bit of each word to be transmitted. A second solution, known as data striping, entails sending a plurality of data words in parallel over multiple conductors in a serial fashion. Each word is transmitted serially over a single conductor, but it is transmitted in parallel with other words on other conductors.
One challenge in implementing a data striping technique for information transmission is the determination of which of the multiple conductors attached to a computer element form the system bus linking one computer element to another. Some prior art systems attempt to use each of the conductors which are physically attached to the computer element. This method has a significant drawback in that if one of the conductors is not operational, the entire bus is rendered inoperable. Other prior art systems have attempted to configure a system bus using only the operational conductors, but these prior ad systems have been driven by hardware switches and have been further limited to system buses of two conductors.
When cache integrity is ensured by links between two elements, there exists a challenge in ensuring that the cache is invalidated when connectivity is lost between the two elements. Prior art systems have stopped both ends of link when either end is suspect.